SE1XK0: Digital Circuits and Design
Module Provider: |
School of Systems Engineering |
Number of credits: |
20 [10 ECTS credits] |
Level: |
C (Certificate) |
Terms in which taught: |
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Module Convenor: |
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Pre-requisites: |
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Co-requisites: |
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Modules excluded: |
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Current from: |
2005/6 |
Aims:
To develop an understanding of digital systems.
To introduce the basic concepts and tools used in digital systems design. |
Assessable learning outcomes:
By the end of the module, it is expected that the student will be able to:
show an appreciation of the fundamental concepts of the digital design process
design and implement combinational logic systems
design and implement simple sequential logic circuits using flip-flops and gates
demonstrate an awareness of the role of VSLI components in the implementation of logic systems
perform logic minimisation
design and implement a finite state machine
write simple behavioural and structural code in a hardware description language |
Additional outcomes:
Experience of:
working with others in a group project
understanding a team approach to projects
problem identification and analysis. |
Outline content:
Quantization and coding Quantizing and sampling. Commonly used codes - binary, hexadecimal, BCD, ASCII, Gray code. Signed number representations.
Logic gates Logical operations, truth tables, binary connectives and Boolean algebra. Implementation. Logic levels in TTL and CMOS. Fan-out, rise time, fall time, propagation delay and noise margins.
Combinational logic design Assignment of logic levels, first and second canonical forms. NAND logic. NOR logic. Don't care conditions. Hazards.
Sequential logic design RS and JK flip-flop, master-slave principle, synchronous and asynchronous triggers, D flip-flop, shift registers. Synchronous and asynchronous sequential designs. Transition maps. Counters and scalers.
VLSI components Logic system implementation strategies. RAM, ROM, (E)PROM, PLA, PAL and FPGA design solutions. Clocking - synchronisation, skew, metastability.
Logic minimisation Karnaugh Maps. Map entered variables. Single and multiple output minimisation using Quine-McClusky.
State machine design Finite state machines. State graphs, ASM charts, state minimisation, identical and equivalent states, incompletely specified machines, state assignment.
Hardware description languages Use of HDLs for the documentation, specification and verification of logic systems. Introduction to the coding of behavioural and structural descriptions using an HDL such as Verilog or VHDL.
Introduction to PLDs and ASICs Overview of ASIC and programmable logic applications. |
Brief description of teaching
and learning methods:
The student will learn from a combination of online materials, group lab work, and formal tutor input. |
Contact hours:
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Over 1 year |
Spring |
Summer |
| Lectures |
30 |
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| Tutorials/seminars |
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| Practicals |
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| Independent Guided Study (including related work at the
work place) |
90 |
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| Total hours |
120 |
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| Practical Project |
1 |
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| Other (eg major seminar paper) |
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Assessment:
The term offered will depend on the partner college
Assessment:
Assessment will be through:
* Continual assessment tests
* Final Exam
* Submission of a Project
Coursework:
The practical project will where possible be related to the work place.
Relative percentage of coursework: 50%
Penalties for late submission:
Penalties for late submission of course work will be in accordance with University policy.
Examinations:
1 * 2 hour test
Requirements for a pass:
Pass in exam and coursework
Reassessment arrangements:
Resubmission of coursework and/or retake examination. |
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