EE3B2: Advanced Digital Design

Module Provider:

School of Systems Engineering

Number of credits:

10 [5 ECTS credits]

Level:

H (Honours)

Terms in which taught:

Autumn

Module Convenor:

Mr CG Guy

Pre-requisites:

SE1A2 EE1A2 CS1C2 or CS1D2 EE2C2 EE2Q2

Co-requisites:

Modules excluded:

Module version for:

2006/7

Aims:
To introduce students to hardware definition languages in general, and VHDL in particular, as a tool for cross-platform design of programmable logic devices.

Assessable learning outcomes:
Students completing this module will appreciate the need for hardware definition languages. They will become familiar with VHDL its ability to define hardware. They will be able to simulate digital designs at different levels from test benches in VHDL. Students will tackle block-level design, modelling and simulation exercises using an industrial VHDL software suite and VHDL behavioural simulator.

Additional outcomes:
A familiarity with the concept of hardware description languages.

Outline content:
1. Hardware description languages for behavioural and structural modelling
2. The IEEE VHDL language for synthesis
3. Simulation methods and test benches
4. Post-layout timing simulation
5. Advanced circuit techniques: retiming, regular arrays and pipelining

Brief description of teaching and learning methods:
Lectures supported by laboratory work

Contact hours:

Assessment:
Coursework
Marked assignments.
Relative percentage of coursework : 20%
Examinations
One 2-hour examination paper in May/June.
Requirements for a pass
40%
Reassessment arrangements
A resit examination the following year