EE2D6: FPGA's and HDL's

Module Provider:

Electronic Engin

Number of credits:

10 [5 ECTS credits]

Level:

I (Intermediate)

Terms in which taught:

Autumn

Module Convenor:

Eur Ing Dr RS Sherratt

Pre-requisites:

SE1EB5 SE1SA5

Co-requisites:

EE2C2

Modules excluded:

Module version for:

2007/8

Aims:
This module aims to introduce students to Verilog as a Hardware Description Language (HDL) for both simulation and with emphasis on synthesis of circuits. Circuits are target to a chosen family of Field Programmable Gate Array (FPGA) for a concise view of the design process from a model to a circuit.

Assessable learning outcomes:
Use of Verilog for describing synthesizable combinational and sequential logic. Description of synthesizable finite state machines (FSM). Design flow methodology for designing with FPGA. Verilog code for simulation in the form of simple test benches is also introduced. Role of pipelining and retiming techniques for speeding up circuits viewed through timing simulation.

Additional outcomes:
Make students aware of the need and importance of design verification.

Outline content:
Detailed view of common design combinational blocks, design of shifting and arithmetic circuits, flip-flops, registers, counters, and memories when targeted to FPGAs. Recommended practices for synthesizing FSMs in FPGAs. Examples of decomposition of designs into controller (FSMs) and datapaths (combinational and sequential processing logic) for a top-down design. The concept of pipelined design units. Examples of retimed circuits to minimize critical combinational paths.

Brief description of teaching and learning methods:
Lectures supported by Lab practicals. First labs are aimed to get familiarity with a vendor FPGA design flow, using real examples from Verilog descriptions to a circuit implemented into a FPGA board. Extra practicals are devoted to a synthesis-based proof of concept from Verilog descriptions in order to identify common limitations of synthesis tools. Dedicated practicals are allocated to the design of state machines using Verilog using real designs that incorporate some human interface. The role of Verilog simulation process and its usage for writing effective simple tes tbenches. Later practicals are designed to work on integration of relatively complex digital systems and evaluation of its real performance. Pipelining and re-timing concepts are introduced and applied to real circuits to demonstrate its capabilities for boosting performance.

Contact hours:

Assessment:
Coursework:
Marked assignments in laboratory sessions.
Relative percentage of coursework : 20%
Examinations:
One 2-hour examination paper in May/June.
Requirements for a pass:
Pass at 40% in combined exam and coursework
Reassessment arrangements:
A resit examination in September